The present invention relates to a level shifter circuit for converting a voltage level in a semiconductor integrated circuit using a plurality of power supply voltages.
Power supply voltages for semiconductor integrated circuits have become lower to reduce power consumption. A semiconductor integrated circuit includes a plurality of circuit blocks having various functions and using various power supply voltages. Further, in a semiconductor integrated circuit, the signal level at an input/output terminal connected to an external device is determined in accordance with the characteristics of the connected device. Thus, power supply voltage that differs from that for internal circuits may become necessary.
Therefore, a semiconductor integrated circuit is supplied with a plurality of power supply voltages. A circuit unit, referred to as a level shifter, for converting signal levels is arranged on portions of a chip of the semiconductor integrated circuit where different power supply regions come into contact with one another (for example, refer to Japanese Laid-Open Patent Publication No. 2001-36398, first page and Japanese Laid-Open Patent Publication No. 2004-96616, FIG. 1). Japanese Laid-Open Patent Publication No. 2001-36398 describes a level shifter circuit including transistors (TP4 and TN4). Signals are input to the transistors to stop signal transmission when fluctuation occurs in the input to the level shifter circuit. Further, a latch circuit is used to stabilize an output signal by outputting a fixed potential that is dependent on an input signal held by the latch circuit.
Japanese Laid-Open Patent Publication No. 2004-96616 describes a level shifter circuit including an N-channel transistor (Mn8) connected between ground and the drains of N-channel transistors (Mn2 and Mn3) in a booster circuit. Low voltage power is applied to the gate of the N-channel transistor (MN8). A bus repeater is connected between the output terminal of the booster circuit and the input terminal of an inverter. When a low voltage power supply is grounded to reduce power supply, the N-channel transistor (Mn8) is deactivated. This prevents tunneling current from flowing in the booster circuit from a high voltage power supply to ground. Even if the potential at the gates of P-channel and N-channel transistors forming the booster circuit fluctuates, the bus repeater holds the output signal of the booster circuit immediately before such a fluctuation. This suppresses fluctuation of the output potential at the level shifter and prevents erroneous operations of circuits connected to the level shifter.
In a situation in which power is supplied to the output side, when power is not supplied to the input side or when power is about to be supplied to the input side, activation of the level shifter may transmit an erroneous signal to the output side. However, in the technique described in Japanese Laid-Open Patent Publication No. 2001-36398, the input side and the output side are separately operated. Thus, control is executed by an input from terminal (C). As a result, a mechanism for controlling the input of terminal (C) in accordance with the state of terminal (A) is necessary.
In the technique described in Japanese Laid-Open Patent Publication No. 2004-96616, a low voltage power supply (VCCL) controls the transistor (Mn8). Since there is not enough margin, the transistor (Mn8) may erroneously operate when the low voltage power supply (VCCL) becomes somewhat high. Thus, normal circuit operation cannot be guaranteed.